Cascade Lake Processors

August 25, 2019 by Adam Jundt

Intel’s latest Xeon line (Cascade Lake) were released in Q2’19. These processors are socket compatible with the previous generation (Skylake), but may require a BIOS update on existing LGA3647 motherboards for support. The main improvements over the previous generation are:

• Increased CPU core counts, clock speeds, and L3 cache
• Support for DDR4-2933 memory
• Introduction of the new AVX-512 VNNI instruction for Deep Learning
• Enhanced Spectre and Meltdown Mitigations

Available SKUs

Intel has announced 58 SKUs ranging from 6 to 56 cores and $213 to $13,000+ (MSRP). The 28 general-purpose SKUs are listed below:

Table showing most commonly used SKUs. Missing from this list are M (medium memory support – 2.0TB), L (large memory support – 4.5TB), Y (speed select models), N (networking/NVF specialized), V (virtual machine density value optimized), T (long life cycle/thermal), U (single socket), and S (search optimized). Note: MSRP is taken from ark.intel.com

Replacement SKUs

Comparing to the similar SKUs from the previous line of processors, we can see that core counts, clock speeds, and cost effectiveness have increased:

Conclusion

The Cascade Lake line of processors increases the core count, clock speeds, L3 cache, at a similar price point to the previous generation, Skylake. If you’re considering purchasing a Xeon processor, we recommend using this latest generation. The CPUs are only a portion of your server selection; RAM, GPUs, storage, networking, chassis, MB, etc. should also be considered.

Contact Us

If you’d like to discuss configuring your next Cascade Lake server, please reach out to me at adam.jundt@advancedhpc.com.

Adam Jundt has worked in High Performance Computing for over 10 years. Starting as a user in grad school (MS in Computer Science with focus on HPC), MPI Developer at Cray, Performance Support at CCT@LSU and SDSC@UCSD for XSEDE researchers, Developer at EP Analytics, and Senior Sales Engineer at Advanced HPC. He has published and presented HPC research at local and international conferences and co-authored proposals that resulted in funding from DOE, DOD, NASA, and NSF. His work has focused on extracting the best energy and performance out of HPC systems and finding matches between application needs and available hardware.